1. Field of the Invention
The present invention relates to structure of capacitors which is capable of improving capacitance of stacked-type capacitors used in DRAMs in accordance with miniaturization of structure of DRAMs and a method of manufacturing the same.
2. Description of the Background Art
One type of semiconductor memory devices includes a DRAM (Dynamic Random Access Memory) which allows random input thereto and output therefrom of storage information. Generally, a DRAM includes a memory cell array which is a storage region storing a number of pieces of information and peripheral circuits necessary for input thereto and output therefrom from and to the outside. FIG. 34 is a block diagram illustrating a structure of a general DRAM. Referring to FIG. 34, a DRAM 50 includes a memory cell array 51 for storing data signals of storage information, a row and column address buffer 52 for receiving an address signal from a circuit for selecting a memory cell which constitutes a unit storage circuit, a row decoder 53 and a column decoder 54 for decoding the address signal to designate a memory cell, a sense refresh amplifier 55 for amplifying and reading the signal stored in the designated memory cell, a data in buffer 56 and a data out buffer 57 for input/output of data, and a clock generator 58 for generating a clock signal.
Memory cell array 51 occupying a large area on a semiconductor chip includes a plurality of memory cells for storing unit storage information arranged in a matrix. FIG. 35 is an equivalent diagram of four bits of memory cells included in memory cell array 51. The illustrated memory cell is what is called a one transistor one capacitor-type memory cell which includes one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected to it. The structure of memory cells of this type is simple, so that the degree of integration of memory cell arrays can be easily enhanced by using them, and they are widely used in DRAMs having large capacity.
Memory cells in DRAMs can be divided into some types according to structure of capacitors. FIG. 36 is a sectional view of structure of a memory cell having a typical stacked-type capacitor, which is described in Japanese Patent Publication No. 60-27845 (1985) and so on, for example. Referring to FIG. 36, the memory cell includes one transfer gate transistor and one stacked-type capacitor (hereinafter referred to as a stacked-type capacitor). The transfer gate transistor includes a pair of source/drain regions 6, 6 formed in the surface of a silicon substrate 1 and a gate electrode (a word line) 4 formed on the surface of silicon substrate 1 with an insulating layer interposed. The stacked-type capacitor includes a lower electrode (a storage node) 11 extending from the upper part of gate electrode 4 to the upper part of a field isolating film 2 and having a part connected to one of source/drain regions 6, 6, a dielectric layer 12 formed on the surface of lower electrode 11, and an upper electrode (a cell plate) 13 formed on the surface of it. A bit line 15 is formed in the upper part of the capacitor with an interlayer insulating layer 20 interposed, and bit line 15 is connected through a bit line contact 16 to the other source/drain region 6 of the transfer gate transistor. The characteristic point of the stacked-type capacitor is that the area between the opposed electrodes of the capacitor is increased by extending the main part of the capacitor to the upper parts of the gate electrode and the field isolating film to secure desired capacitance of the capacitor.
Generally, capacitance of a capacitor is directly proportional to the area between opposed electrodes and inversely proportional to the thickness of dielectric layer. Accordingly, it is desirable that the area between the opposed electrodes of a capacitor is increased to increase capacitance of a capacitor. On the other hand, the size of a memory cell has been largely reduced in accordance with large scale integration of a DRAM. Therefore, the flat occupied area of a capacitor forming region has also been reduced. However, it is not possible to reduce the amount of electric charge which can be stored in a memory cell of one bit in consideration of stable operation or reliability of DRAM as a memory device. In order to satisfy such directly-opposed conditions, various types of improvements in a structure of a capacitor capable of reducing the flat occupied area of a capacitor and increasing the area between opposed electrodes are proposed.
FIG. 37 is a cross sectional view of a structure of a memory cell including a stacked-type capacitor disclosed in JP2-122560, for example. Referring to FIG. 37, a transfer gate transistor 3 includes a gate electrode 4 having its periphery covered with an insulating layer 22, a pair of source/drain regions 6, 6, and a gate oxide film 5. A stacked-type capacitor 10 includes a lower electrode 11, a dielectric layer 12, and an upper electrode 13. Lower electrode 11 includes a base part 11a formed on the surfaces of insulating layers 22, 22 covering gate electrodes (word lines) 4, 4 and a projecting part 11b extending from the surface of base part 11a upward. Dielectric layer 12 and upper electrode 13 are sequentially layered on the surface of lower electrode 11. The illustrated stacked-type capacitor uses the surface of projecting part 11b of lower electrode 11 as an charge storage region. Projecting part 11b makes it possible to increase the capacitance of the capacitor without increasing the plane occupied area of the capacitor.
FIGS. 38-42 are cross sectional views illustrating structure of the memory cell illustrated in FIG. 37 in a main manufacturing process.
First, referring to FIG. 38, a polycrystalline silicon layer is formed on the whole surface of a substrate, and then, impurities are introduced thereinto. Etching is carried out using a resist pattern 30 as a mask to form a lower electrode 110a.
Then, referring to FIG. 39, resist pattern 30 is removed, and then, a polycrystalline silicon layer 110b is formed on the whole surface. Impurities of a low concentration are introduced from lower electrode 110a into polycrystalline silicon layer 110b.
Then, referring to FIG. 40, anisotropic etching is carried out on polycrystalline silicon layer 110b and lower electrode 110a by RIE. In the etching process, first, anisotropic etching is carried out on polycrystalline silicon layer 110b to leave polycrystalline silicon layer 110b only on the side surfaces of the lower electrode. Then, lower electrode 110a is sequentially etched from the upper surface. The etching is ended when lower electrode 110a has been etched to have a predetermined thickness. Base part 11a and projecting part 11b of lower electrode 11 are formed by those steps.
Then, referring to FIG. 41, a dielectric layer 12 and an upper electrode 13 are formed on the surface of the lower electrode.
However, base part 11a and projecting part 11b of lower electrode 11 in the stacked-type capacitor are formed by different steps. Accordingly, a seam is formed on the boundary between base part 11a and projecting part 11b. A natural oxide film is liable to form on the seam after formation of base part 11a. Therefore, there is a case where electric conduction between base part 11a and projecting part 11b is prevented by the natural oxide film, so that projecting part 11b does not function as a lower electrode of the capacitor.
The upper surface of projecting part 11b on which anisotropic etching has been carried out is illustrated as flat in FIGS. 39 and 40. However, according to the inventor's knowledge, the etched upper surface of projecting part 11b is formed in a shape in which the inner peripheral side is sharp as illustrated in FIG. 42. If such a sharp angular part is formed, electric field concentration occurs in that part to cause a problem of dielectric breakdown of dielectric layer 12.